1. Field of the Invention
The present invention relates to a serial data transfer system having a plurality of semiconductor chips for serially sending and receiving data between the chips in synchronism with a single serial clock pulse and, more particularly, to a serial data transfer system using a single clock line and a single data line for sending and receiving serial data in synchronism with the serial clock pulse while confirming the data reception.
2. Description of the Prior Art
There are two methods for transferring data between a plurality of semiconductor chips (which will be shortly referred to as the "LSI chips"): one using data buses of eight or sixteen bits; and the other using a single data line in a time sharing manner to transfer the data in series bit by bit. The latter method is remarkably convenient for connecting the LSI chips because only two lines are required for these connections: a data line and a clock line.
However, it cannot be said that the serial data transfer system can complete the serial transfer merely through the two signal lines or the serial clock and data lines. In order to ensure the serial transfer through one data line, more specifically, it is necessary not only that the start and end of the transfer should be able to be correctly detected but also that it should be confirmed whether or not the data sent from the transmitting side have been correctly received by the receiving side. For this confirmation, another signal line should have been used in the prior art. This means that the serial transfer could not be executed merely by the two signal lines of the serial clock and data lines.
In another aspect, the second serial data processor of the serial data transfer system specified above does not send any reception confirmation signal to the first serial data processor after it has received the serial data of eight bits (or one byte). The prior art fails to provide any means for informing the transmitting side of a rejection to the reception of continuous serial data of plural bytes being transferred, even in case the reception is desired because of some malfunction occurring at the receiving side. In order to eliminate this difficulty, the receiving side has to be programmed to output the reception confirmation signal to the transmitting side if it ends the processing of the data received. According to this method, however, the receiving side has also to be programmed to generate the reception confirmation signal each time it receives one byte. This raises a serious defect that the processing efficiency of the CPU used is seriously deteriorated.